Table of Contents

Chapter 1: Verification Tools and Methodologies 3

1.1 Setting the Stage 3

1.1.1 Design Flow: From Intent to Product 4

1.1.1.1 Transaction Level Modeling and Design Abstraction Levels 5

1.1.1.2 Design Implementation Flow 6

1.1.2 Functional Verification: Gaining Closure 7

1.1.2.1 Black-Box, White-Box, and Gray-Box Verification 8

1.1.3 The Verification Challenge 10

1.2 Verification Metrics 12

1.2.1 Granularity 12

1.2.2 Manual Effort 13

1.2.3 Effectiveness 14

1.2.4 Completeness 14

1.2.5 Verification Environment Reusability 14

1.2.6 Simulation Result Reusability 15

1.3 Interaction between Design and Verification 15

1.4 Verification Technologies 16

1.4.1 Formal Verification 17

1.4.1.1 Equivalence Checking 17

1.4.1.2 Formal Property (Assertion) Checking 18

1.4.2 Simulation-Based Verification 19

1.4.3 Acceleration and Emulation 20

1.5 Verification Methodologies 21

1.5.1 Assertion-Based Verification 21

1.5.1.1 Assertion Evaluation and Tool Flow 22

1.5.1.2 White-Box vs. Black-Box Assertions 24

1.5.2 Coverage-Driven Verification 24

1.5.2.1 Transaction-Driven Verification 25

1.5.2.2 Constrained Random Generation 26

1.5.2.3 Automatic Result Checking 28

1.5.2.4 Coverage Collection 28

1.5.2.5 Directed Tests 29

1.5.2.6 Coverage-Driven Verification Project Life Cycle 29

1.5.3 Metric-Driven Verification 30

Chapter 2: Verification Planning 31

2.1 The Modern Verification Plan 31

2.1.1 Verification Planning Challenges 32

2.1.2 Verification Planning Goals 34

2.1.3 Verification Plan Contents 34

2.1.4 Verification Project Cycle: Gaining Closure 35

2.2 Building the Verification Plan 35

2.2.1 Identify Actors 36

2.2.2 Preparing to Start the Brainstorming Session 37

2.2.3 Brainstorm about the Content 38

2.2.4 Verification Plan Structure 38

2.2.4.1 Verification Plan Outline 38

2.2.4.2 Verification Views 39

2.2.4.3 Verification Scenario Details 40

2.2.4.4 Verification Build and Run Infrastructure 40

2.2.5 Capturing Features 41

2.2.6 Capturing Attributes 41

2.3 From Plan to Environment 42

2.3.1 Identifying Required Stimulus 42

2.3.2 Identifying Required Checkers and Collectors 43

2.4 Measuring Progress 43

2.5 Reacting to Results 43

Chapter 3: Verification Environment Architecture 45

3.1 Abstract View of a Verification Environment 45

3.2 Interface Verification Components 47

3.2.1 Logical View 48

3.2.2 Driver 49

3.2.2.1 Feature Set 50

3.2.2.2 User Interface 51

3.2.3 Sequencer 52

3.2.4 Agent and Bus Monitors 53

3.3 Software Verification Components 54

3.4 Module/System Verification Components 55

3.4.1 Sequencer 57

3.4.1.1 Initialization 57

3.4.1.2 Configuration 58

3.4.1.3 Scenario Generation and Driving 58

3.4.2 VE Monitor 58

3.4.3 DUV Monitor and Assertion Checker 59

3.4.4 Scoreboarding 60

3.4.5 Coverage Collector 61

3.5 Verification Component Reuse 61

Chapter 4: SystemVerilog as a Programming Language 65

4.1 The Generalized Model of a Digital System 65

4.2 Structure of a SystemVerilog Program 67

4.2.1 Hierarchies of Different Types 69

4.3 Data Types and Objects in SystemVerilog 69

4.3.1 Data Lifetime 70

4.3.2 Update Mechanisms 71

4.3.3 Data Types 71

4.3.3.1 Built-In Data Types 72

4.3.3.2 Enumerated Data Types 74

4.3.3.3 Arrays 75

4.3.3.3.1 Static Arrays 76

4.3.3.3.2 Dynamic Arrays 77

4.3.3.3.3 Associative Arrays 78

4.3.3.3.4 Queues 80

4.3.3.4 Composite Data Types 81

4.3.3.5 User Defined Data Types 82

4.3.4 Operators 83

4.4 Procedural Statements and Blocks 84

4.4.1 Assignment Statements 84

4.4.2 Subroutine Calls 85

4.4.2.1 Functions 85

4.4.2.2 Tasks 87

4.4.3 Selection Statements 88

4.4.3.1 If-Else Statements 88

4.4.3.2 Case Statements 89

4.4.3.3 Random Case Statements 90

4.4.4 Loop and Jump Statements 90

4.4.5 Event Control Statements 91

4.5 Module Hierarchy 91

4.5.1 Modules and Module Ports 93

4.5.1.1 Port Connection Syntax 94

4.5.1.2 Port Connection Rules 94

4.5.2 Interface Blocks 95

4.5.3 Parameters 99

4.5.4 Hierarchical Names 100

4.6 Processes and Execution Threads 100

4.6.1 Static Processes 101

4.6.2 Dynamic Processes 101

4.7 Object-Oriented Programming and Classes 101

4.7.1 Static Properties and Methods 104

4.7.2 Class Hierarchy, Inheritance, and Abstract Classes 105

4.7.2.1 Parent Class Scope: Super 106

4.7.2.2 Abstract Classes 106

4.7.2.3 Virtual Methods 107

4.7.2.4 Out of Block Declarations 108

4.7.3 Parameterized Classes 108

4.7.4 Polymorphism: Uniform Access to Diverse Objects 109

4.7.5 Data Hiding 110

Chapter 5: SystemVerilog as a Verification Language 113

5.1 Scheduling Semantics 114

5.1.1 Active Region 115

5.1.2 Inactive Region 115

5.1.3 NBA Region 116

5.1.4 Observed Region 116

5.1.5 Reactive Region 116

5.1.6 Postponed Region 117

5.2 Clocking Blocks 117

5.2.1 Input and Output Skews 120

5.2.2 Default Clocking 121

5.3 Program Block 121

5.4 Inter-Process Communication and Synchronization 125

5.4.1 Events 125

5.4.2 Semaphores 127

5.4.2.1 Semaphore for Mutual Exclusion 127

5.4.2.2 Thread Rendezvous 128

5.4.3 Mailboxes 130

5.5 Constrained Random Generation 131

5.6 Property Specification and Evaluation 131

5.7 Coverage Collection 131

Chapter 6: OVM Infrastructure 135

6.1 Verification Class Library Goals 136

6.2 OVM Class Library Features 137

6.3 Object and Component Factories 140

6.3.1 Type and Instance Overrides 141

6.3.2 OVM Object Factory 142

6.3.3 OVM Component Factory 145

6.4 Field Automation 147

6.5 Core Utilities 149

6.5.1 Copy 150

6.5.2 Compare 151

6.5.3 Print 153

6.5.4 Packing and Unpacking 155

6.5.4.1 Packing and Unpacking of Automated Fields 159

6.5.4.2 Packing and Unpacking Metadata 159

Chapter 7: OVM Component Hierarchy 161

7.1 Abstract View of the Component Hierarchy 161

7.2 Hierarchy and Configuration Constructs 164

7.3 Verification Environment Component Types 169

7.3.1 Verification Environment Components 169

7.3.2 OVM Models of Verification Environment Components 172

7.4 Simulation Phase Control 174

7.4.1 Starting the Simulation Phases 175

7.4.2 Stopping the Simulation Run Phase 176

Chapter 8: OVM Transaction Sequences 181

8.1 Verification Scenarios and Sequences 182

8.2 Sequencers 184

8.2.1 Sequence Items 185

8.2.2 Sequencer Declaration 186

8.3 Sequences 187

8.4 Hierarchical Sequences 189

8.5 Sequence Library 192

8.5.1 Predefined and User Defined Sequences 192

8.6 Executing Sequences and Sequence Items 193

8.6.1 Executing Root Sequences and Subsequences using Methods 193

8.6.2 Executing Subsequences and Sequence Items using Macros 195

8.7 Sequence Item Interfaces 198

8.8 Sequencer Arbitration Mechanism 199

8.8.1 Sequence Interaction 200

8.8.2 Sequence Selection 200

8.9 Virtual Sequencers 202

8.10 Sequence Interfaces 203

Chapter 9: OVM Transaction Interfaces 207

9.1 Transaction Connector Objects 209

9.2 Binding Connector Objects 211

9.3 Unidirectional Interfaces 213

9.4 Bidirectional Interfaces 219

9.5 Analysis Interface 224

9.6 Multiple Connector Objects in One Component 228

9.7 Transaction Channels 229

9.7.1 TLM FIFO Channel 231

9.7.2 Analysis FIFO Channel 232

9.7.3 Request/Response Channel 233

Chapter 10: Constrained Random Generation 237

10.1 Random Generators and Constraint Solvers 237

10.1.1 Constrained Randomization and Variable Ordering Effects 238

10.1.2 Random Generation Engine 241

10.2 Randomization in SystemVerilog 243

10.2.1 Random Variables 244

10.2.2 Random Dynamic Arrays 246

10.2.3 Constraint Blocks 247

10.3 Constraint-Specific Operators 249

10.3.1 Set Membership Constraints 249

10.3.2 Distribution Constraints 250

10.3.3 Implication Constraints 250

10.3.4 If-Else Constraints 251

10.3.5 Iterative Constraints 252

10.3.6 Global Constraints 253

10.3.7 Variable Ordering Constraints 254

10.3.8 Function-Call Constraints 255

10.4 Constraint Guards 255

10.5 Controlling Constrained Randomization 257

10.5.1 Controlling Constraints 257

10.5.2 Disabling Random Variables 258

10.5.3 Randomization Flow Methods 259

10.6 Random Stability 261

10.7 System Functions 264

10.7.1 $urandom 264

10.7.2 $urandom_range() 264

10.7.3 srandom() 264

Chapter 11: Data Modeling 267

11.1 Data Models in SystemVerilog 268

11.2 Data Model Fields and Constraints 269

11.2.1 Data Model Fields 269

11.2.2 Data Model Constraints 271

11.3 Hierarchical Models 273

11.4 Data Model Subtypes 274

11.5 Data Model Views 277

11.5.1 Method View 278

11.5.2 Constraint View 278

11.5.2.1 Abstract Ranges 278

11.5.2.2 Coordinated Ranges 279

11.5.2.3 Default Ranges 279

11.6 Transactions: Command and Status 280

Chapter 12: Module-Based VE Implementation 283

12.1 Module-Based Implementation Overview 284

12.2 XBar Design Specification 286

12.3 XBar VE Architecture 288

12.4 DUV Wrapper 289

12.5 Library Package 290

12.6 XBar Data Packet 292

12.7 Transaction Interfaces 292

12.8 Event Interfaces 294

12.9 Building the Hierarchy 295

12.10 Monitor 298

12.11 Driver 300

12.12 Sequencer 301

12.13 Scoreboarding 304

12.14 Test Component 306

12.15 Modifying Sequencer Default Behavior 307

Chapter 13: Class-Based VE Implementation 309

13.1 Class-Based Implementation Overview 309

13.2 XBar Data Packet 311

13.3 Physical Interfaces 312

13.4 Transaction Ports and Interfaces 313

13.5 Event-Based Synchronization 314

13.6 Building the Hierarchy 315

13.6.1 XBar Receive Agent 316

13.6.1.1 Receive Monitor 316

13.6.1.2 Receive Sequencer 318

13.6.1.3 XBar Driver 320

13.6.1.4 XBar Agent Top Level Component 321

13.6.2 XBar Transmit Agent 322

13.6.3 XBar Interface VC 322

13.6.4 XBar Verification Environment 324

13.6.5 XBar Tests 325

13.6.6 XBar Testbench 327

13.7 Monitor Run Phase 328

13.8 Driver Run Phase 329

13.9 Sequencer 330

13.10 Scoreboarding 331

13.10.1 Implementation with User Defined Analysis Imp Types 331

13.10.2 Implementation with Listener Subcomponents 332

Chapter 14: Verification Scenario Generation 337

14.1 XBar Communication Protocol 337

14.2 XBar Transfer and Frame Models 339

14.3 XBar Sequence Generation Architecture 340

14.4 Flat Sequences 343

14.4.1 Sequencer Default Behavior 345

14.4.2 Adding Sequences to the Sequence Library 346

14.4.3 Modifying the Default Behavior 347

14.5 Hierarchical Sequences 348

14.6 Reactive Sequences 350

14.7 Virtual Sequences 352

14.7.1 Virtual Sequencer 354

14.7.2 Sequence Interface Connectivity 355

14.7.3 Downstream Sequences 356

14.7.4 Virtual Sequence Library 356

14.8 Grabber Sequences 358

14.9 Layered Sequences 361

14.10 Conditional Sequences 364

14.11 Sequence Synchronization with End of Run 367

Chapter 15: Property Specification and Evaluation Engine 371

15.1 Property Specification Hierarchy 372

15.2 Boolean Expressions 374

15.2.1 Operand Types 374

15.2.2 Operators 375

15.2.3 Sampling Events 375

15.2.4 Operand Value Sampling: Sampled Value vs. Current Value 375

15.2.5 Sampled Value Functions 376

15.3 Sequences 377

15.3.1 Sequence Declarations and Formal Arguments 379

15.3.2 Sequence Evaluation Model 381

15.3.2.1 Evaluation Sub-Threads and Multiple Matches 382

15.3.3 Sequence Operators 383

15.3.3.1 Sequence Delay Repeat Operators 383

15.3.3.2 Sequence Repeat Operators 384

15.3.3.3 Sequence AND Operator 386

15.3.3.4 Sequence OR Operator 387

15.3.3.5 Sequence INTERSECT Operator 387

15.3.3.6 Sequence THROUGHOUT Operator 388

15.3.3.7 Sequence WITHIN Operator 389

15.3.3.8 Sequence �gfirst_match�h Operator 389

15.4 SystemVerilog Properties 390

15.4.1 Property Declarations and Formal Arguments 390

15.4.2 Property Evaluation Model 391

15.4.2.1 Evaluation Threads: Properties and Sequences 393

15.4.2.2 Property Evaluation Start Points 393

15.4.2.3 Properties and Degenerate Sequences 395

15.4.3 Property Operators 396

15.4.3.1 Boolean Operators 397

15.4.3.2 Implication Operators 397

15.5 Base Operators vs. Derived Operators 400

15.6 Multi-Clock Sequences and Properties 401

15.6.1 Semantic Requirements 402

15.7 Sequence and Property Dictionary 404

15.7.1 Sequence Dictionary 404

15.7.1.1 Sequences Based on One Condition 405

15.7.1.2 Sequences Based on Two Conditions 406

15.7.1.3 Sequences Based on Multi-Cycle Behaviors 407

15.7.2 Property Dictionary 408

15.7.2.1 Properties using a Condition as a Qualifying Condition 409

15.7.2.2 Properties using a Multi-Cycle Behavior as a Qualifier 409

15.7.2.3 Properties Used for Debugging Sequences 410

Chapter 16: Assertion-Based Verification (ABV) 411

16.1 Assertion Definition Flow 412

16.1.1 Participants and Roles 412

16.1.2 Assertions and Project Phases 413

16.1.2.1 Architectural Design 413

16.1.2.2 Block Design and Verification 413

16.1.2.3 Cluster/Chip Integration and Verification 414

16.1.2.4 System Integration and Verification 415

16.2 Assertions vs. Assumptions 415

16.3 SystemVerilog Assertions 417

16.3.1 Assertion Activation 417

16.3.1.1 Immediate Assertions 417

16.3.1.2 Concurrent Assertions 418

16.3.1.2.1 Procedural Assertions 419

16.3.2 Severity System Tasks 421

16.3.3 Assertion Control System Tasks 421

16.4 Capturing Assertion Requirements 422

16.4.1 Step 1: Consider Verification Objectives 422

16.4.2 Step 2: Partition the Problem 423

16.4.2.1 Interface 423

16.4.2.1.1 Configuration 424

16.4.2.1.2 DUV Input Pins 424

16.4.2.1.3 Protocol 425

16.4.2.1.4 Register Interface 426

16.4.2.2 Core Function 426

16.4.2.3 Design Outputs 426

16.4.3 Step 3: Identify Requirements for Each Partition 427

16.4.4 Step 4: Map Requirements to Assertion Forms 427

16.4.5 Step 5: Define Clocking and Reset/Interrupt Conditions 428

16.4.6 Step 6: Add the Assertions to the Design 428

16.5 Assertion-Based Verification IPs 429

16.5.1 Assertion Libraries 429

16.5.1.1 Assertion Library Component Architecture 430

16.5.1.2 Using Assertion Library Components 431

16.5.2 Assertion-Based Protocol Checkers 431

16.5.2.1 Assertion-Based Protocol Checker Architecture 432

Chapter 17: Coverage Collection Engine 435

17.1 Coverage Collection Overview 436

17.2 Coverage Groups 438

17.2.1 Coverage Group Activation 439

17.3 Coverage Points and Transitions 439

17.3.1 Coverage Point Sampling Semantics 441

17.3.2 Coverage Point Value and Transition Bins 443

17.3.2.1 Coverage Point Value Bins 443

17.3.2.2 Coverage Point Transition Bins 446

17.4 Cross Coverage Elements 448

17.4.1 Cross Coverage Bins 450

17.5 Class-Based Coverage Collection 452

17.6 Coverage Options 454

17.7 Coverage Methods 454

17.8 Assertion-Based Coverage 455

Chapter 18: Coverage Planning, Implementation, and Analysis 457

18.1 XBar Verification Plan 458

18.2 Coverage Design 460

18.2.1 Coverage Collection Glue Logic 460

18.2.2 Cross Coverage Implementation Models 462

18.2.2.1 Multi-Instance Coverage Models 462

18.2.2.2 Multidimensional Coverage Models 464

18.2.2.3 Multi-Definitional Coverage Model 466

18.2.2.4 Hierarchical Coverage Models 468

18.2.3 Transition Coverage Implementation 469

18.3 Coverage Grading 470

18.4 Coverage Analysis 471