"This detailed, step-by-step guide provides a thorough
introduction to SystemVerilog and the Open Verification
Methodology (OVM). With many examples and clear
descriptions, it should be helpful to anyone involved
in IC functional verification."
"Dr. Iman brings together all the essential elements to
understand the use and application of OVM. Those with
limited SystemVerilog knowledge will find Step-by-Step
Functional Verification with SystemVerilog and OVM
offers a complete introduction to SystemVerilog, and
the SystemVerilog-savvy will find this a comprehensive
OVM reference. This book has everything design and
verification engineers would want to know to apply
OVM to their most pressing challenges."
Director of Strategic Business Development
Mentor Graphics Corporation
"The author of this book is well known in the design
community as a leader in the verification space.
SystemVerilog has provided a major step in our
capability to verify our designs, especially in today’s
world of 40 million gate SoCs. The combination has
produced a very thorough step by step guide to the
latest in verification methodology."
Gary Smith EDA
"The Open Verification Methodology (OVM) is one of
the most quickly and widely adopted new solutions
ever for verifying complex chips. This book walks the
reader through the OVM as well as the SystemVerilog
language constructs upon which it is built. The
breadth of Step-by-Step Functional Verification with
SystemVerilog and OVM and its pragmatic approach
make it an invaluable resource for both novice and
experienced verification engineers."
Chief Technology Officer
Cadence Design Systems
This book is intended for a wide range of readers. It can be used to learn functional verification methodology, the SystemVerilog language, and the OVM class library and its methodology. This book can also be used as a step-by-step guide for implementing a verification environment. In addition, the source code for the full implementation of the XBar verification environment can be used as a template for starting a new project. As such, this book can be used by engineers starting to learn the SystemVerilog language concepts and syntax, as well as advanced readers looking to achieve better verification quality in their next verification project. This book can also be used as a reference for the SystemVerilog language and the OVM class library. All examples provided in this book are fully compliant with SystemVerilog IEEE 1800 standard and should compile and run on any IEEE 1800-compliant simulator.